A dynamically reconfigurable logic circuit device includes a plurality of
dynamically reconfigurable processor units (DRPU) arranged in array, and
a plurality of dynamically connecting units (DCU). The dynamically
connecting units interconnect inputs and outputs of the dynamically
reconfigurable processor units. Each of the dynamically reconfigurable
processor units includes a plurality of arithmetic processing
configurations, a plurality of input data storage units, and a plurality
of output data storage units. The arithmetic processing configurations,
input data storage units, and output data storage units are both selected
and set up in accordance with an interrupting signal from an interrupt
controller. Similarly, the interconnection of the dynamically
reconfigurable processor units through the dynamically connecting units
is performed in accordance with the interrupting signal. The above
structure is operable to change input data as well as the arithmetic
processing configurations upon the issuance of a request for interrupt
from a CPU, and to change the entire logic circuit configuration. As a
result, time-division multiplexing is achievable.
