A method and apparatus for extracting circuit design information from a pre-existing
semiconductor integrated circuit (IC) or at least a portion thereof is described.
It includes imaging at least a portion of two or more physical layers of the pre-existing
IC to obtain stored electronic images of the physical IC layers, converting the
stored electronic images of the physical IC layers to a vector format data, horizontally
and vertically aligning the vector format data of the electronic stored images
of the physical IC layers, and providing a multi-layer display of the aligned vector
format data. A net-list or schematic is generated from the multi-layer display
of the vector format data. The net-list and/or schematic may be generated as a
number of individual pages by providing a template of circuit elements and placing
a circuit element over a portion of the display corresponding to the circuit element.
The template of circuit elements may include transistors, logic gates or complex
circuit blocks. The vector format data may be altered to correct errors in the
images or manipulated to correct the alignment of the images. In addition, the
schematic may be traced to the image of the physical IC layer.
