An EEPROM cell device on a substrate is achieved. The device comprises, first,
a selection transistor having gate, drain, source, and channel. The drain is defined
as a cell bit line. An isolation transistor has gate, drain, source, and channel.
The source is defined as a cell source line. Finally, a floating gate transistor
has control gate, floating gate, drain, source, and channel. The drains and sources
of each transistor comprise a diffusion layer in the substrate. The channels of
each transistor comprise the substrate. The floating gate transistor drain is coupled
to the selection transistor source. The floating gate transistor source is coupled
to the isolation transistor drain. The device is programmed and erased by charge
tunneling between the floating gate and the floating gate transistor channel. The
device may further comprise an isolation well underlying the diffusion layer. A
two transistor EEPROM cell is disclosed. Several array architectures using the
EEPROM cell are disclosed.
