Methods and apparatus are provided for an analog converter. The apparatus
comprises a first redundant signed digit (RSD) stage and a configurable block.
The configurable block converts to a sample/hold circuit to sample a single ended
analog signal. The sampled signal is then scaled, converted to a differential signal
and provided to the first RSD stage. The first RSD stage outputs a bit value corresponding
to the magnitude of the digital signal. In a next half clock cycle the first RSD
stage calculates a residue that is provided to the configurable block. The configurable
block is converted to a second redundant signed digit stage and generates a bit
value corresponding to the magnitude of the residue provided by the first RSD stage.
The first and second RSD stages cycle back and forth generating logic value each
half clock cycle until the desired bit resolution is achieved. The configurable
block is then converted back to a sample/hold circuit to start another conversion process.
