Scheme to encode predicted values into an instruction stream/cache without additional bits/area

   
   

Methods, articles of manufacture and systems for encoding an instruction are provided, whereby available bits within the instruction can be indicated for use. The available bits may include zero bits and constant bits. In one embodiment available bits include any bits within an expanded word that are not necessary for the execution of an instruction contained in the word. In another embodiment, bits are made available by reformatting/re-encoding a word, whereby the number of bits of some fields is abbreviated to a lesser number of bits.

 
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< Method, system and program product comprising breakpoint handling mechanism for debugging and/or monitoring a computer instruction sequence

> Secondary trace build from a cache of translations in a caching dynamic translator

> Method of optimizing high performance CMOS integrated circuit designs for power consumption and speed using global and greedy optimizations in combination

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