A non-linear, gain-based modeling of circuit delay within an electronic design
automation system. The present invention provides a scalable cell model for use
in early logic structuring and mapping for the design of integrated circuits. The
scalable cell model includes a four dimensional delay model accepting input slew
and gain and providing delay and output slew. By eliminating output loading as
a requirement for delay computations, the scalable model of the present invention
can effectively be used to provide accurate delay information for early logic synthesis
processes, e.g., that precede technology dependent optimizations where the actual
load of a cell is unknown. This scalable cell model considers: the impact of transition
times on delay; complex gates having different input capacitances for different
input pins; the impact of limited discrete cell sizes in the technology library;
and design rules, e.g., maximum capacitance and maximum transition associated with
gates. A technology library is analyzed and clustering is performed to select a
cluster of cells for each cell group of a common functionality. A nominal input
slew value is computed for all cells and a scaling factor is computed for each
cell of each cluster. From each cluster, a four dimensional gain-based non-linear
scalable cell model (look-up table) is generated. A default gain is computed for
each scalable cell model and an area model and an input pin capacitance model are
generated for each scalable cell model.
