A processing state that enables a processor to resume processing operations before
completion of a processor-issued data move operation. The processor executes instructions
specifying a data clone operation and delays subsequent instruction execution while
waiting for a receipt of an indication that the data clone operation has completed.
In response to the instructions, a memory cloner issues a series of naked write
operations targeting the destination memory location and tracks receipt of Null
responses for each of the naked write operations. When a Null response has been
received for each of the naked write operations, the memory cloner transmits an
acknowledgment to the processor indicating that the write operation is architecturally
complete before the actual data move has completed. In response to receiving the
acknowledgment, the processor resumes execution of subsequent instructions in the
instruction stream.
