Memory access collision avoidance scheme

   
   

A method and a circuit for avoiding memory access collisions during asynchronous read-write access to a single-port RAM (SPRAM) are described. Serial write access by means of a serial interface and read access with a read strobe from an independent read device are generated asynchronously. Prerequisites for the implementation are: firstly, use of a serial interface providing a serial clock signal; secondly, write access to SPRAM has to occur at the end of serial transmission; thirdly, a write strobe impulse has to be short compared to the original read strobe. Energy saving is achieved by guaranteeing only one regular read strobe, even when multiple write accesses occur during one read access. The read strobe signal can therefore be used also for control of an LCD backplane counter.

 
Web www.patentalert.com

< Data reproduction system, data recorder and data reader preventing fraudulent usage by monitoring reproducible time limit

< Cross-clock domain data transfer method and apparatus

> System and method for managing off-screen buffers for electronic images

> Method and system for creating secure address space using hardware memory router

~ 00191