A present invention provides a system and method for avoiding memory hazards
in
a multi-threaded CPU which shares an L-1 data cache. The system includes a CPU
and an AACAM. The AACAM is capable of copying memory addresses from the two or
more threads being processed by the CPU. The method provides for comparing the
AACAM memory address with the active threads to avoid memory hazards by thread
switching before the memory hazard occurs.
