An output circuit of an integrated circuit device includes first and second MOS
transistors including respective spaced apart pairs of source and drain regions
in a substrate, arranged such that respective first and second channels of the
first and second MOS transistors are laterally displaced with respect to one another.
The output circuit further includes an isolation region in the substrate, disposed
between the first and second MOS transistors. A first conductor connects the source
region of the first MOS transistor to a power supply node. A second conductor connects
the drain region of the first MOS transistor to the source region of the second
MOS transistor. A third conductor connects the drain region of the second MOS transistor
to an external signal pad of the integrated circuit device. The isolation region
may comprise first and second insulation regions surrounding respective ones of
the first and second MOS transistors, and a guard ring surrounding and separating
the insulation regions.
