A computer has instruction pipeline circuitry capable of executing two
instruction set architectures (ISA's). A binary translator translates at
least a selected portion of a computer program from a lower-performance
one of the ISA's to a higher-performance one of the ISA's. Hardware
initiates a query when about to execute a program region coded in the
lower-performance ISA, to determine whether a higher-performance
translation exists. If so, the about-to-be-executed instruction is
aborted, and control transfers to the higher-performance translation.
After execution of the higher-performance translation, execution of the
lower-performance region is reestablished at a point downstream from the
aborted instruction, in a context logically equivalent to that which
would have prevailed had the code of the lower-performance region been
allowed to proceed.
