A floating gate field-effect transistor (400), which is preferably used
as a memory cell, has, above or below a floating gate region (407), an electrically
insulating layer sequence (408) having a lower layer (409) having
a first relative permittivity, having a middle layer (410) having a second
relative permittivity, and having an upper layer (411) having a third relative
permittivity, the second relative permittivity being greater than the first relative
permittivity and greater than the third relative permittivity.
