An apparatus and method which block the strobing of a data FIFO array in a memory
controller of a computer system after the data strobe has entered a fluctuating
tristate phase, in particular in the setting of a system using double date rate
(DDR) DRAM devices. Such a system generally includes DIMMs (dual in-line memory
modules) driven by, and driving, data strobes over a bidirectional bus. Because
of the use of a bus instead of point-to-point connections, the data strobes are
allowed to fluctuate in a tristate phase, during which time false strobes could
corrupt data in an input FIFO array coupled to a requesting device before capture
of requested data. A circuit is presented which enables a masking circuit to allow
passage of the strobe signals in response to a gate reset signal generated by the
memory controller, but subsequently blocks the strobe signals before the strobe
enters its tristate phase.
