Information specifying invalidating areas of a main memory is stored
in an area specifying register. Each time a signal indicating an index address
is input to a tag memory and a data memory, cached data of the index address of
a data memory is output, a tag address is output from a tag memory. A combined
address of the tag address and the index address indicates an address of the main
memory from which data is written at the index address of the data memory. Thereafter,
it is judged whether or not an area of each combined address of the main memory
agrees with one of the invalidating areas. In case of the agreement of the area
of each combined address and one invalidating area, the invalidating processing
is performed for the cached data of the index address corresponding to the combined address.
