In a computer architecture using a prevalidated tag cache design, logic circuits
are added to enable store and invalidation operations without impacting integer
load data access times and to invalidate stale cache lines. The logic circuits
include a translation lookaside buffer (TLB) architecture to handle store operations
in parallel with a smaller, faster integer load TLB architecture. A store valid
module, added to the TLB architecture, sets a valid bit when a new cache line is
written. The valid bit is cleared on the occurrence of an invalidation operation.
The valid bit prevents multiple store updates or invalidates for cache lines that
are already invalid.
