A CPU model issues a memory access request to a memory control circuit by executing
a verification test program. A transaction monitor monitors a transaction generated
on a system bus, and detects and holds a transaction of memory access from the
CPU model. A memory model responds to access from the memory control circuit, and
acquires transaction information of that access. A memory access checker logically
verifies the memory control circuit using the transaction information acquired
by the memory model, and the transaction information held by the transaction monitor.
