Embodiments of the present invention provide a memory controller comprising
a front-end module, a back-end module communicatively coupled to the front-end
module, and a physical interface module communicatively coupled to the back-end
module. The front-end module generates a plurality of page packets from a plurality
of received memory commands, wherein the order of receipt of said memory commands
is preserved. The back-end module dynamically issues a next one of the plurality
of page packets while issuing a current one of the plurality of page packets. The
physical interface module causes a plurality of transfers according to the dynamically
issued current one and next one of the plurality of page packets.
