In a delay adjusting unit arranged in a clock delay adjusting circuit, when a
drive power switch signal is at an "H" level, a transfer gate is closed, and an
input signal is delayed by a delay amount of the delay unit. When drive power switch
signal is at the "L" level, the transfer gate is closed, and the input signal is
output without being delayed. When the current drive power of an output buffer
is low, the drive power switch signal at the "L" level decreases the delay amount
of an output clock signal. When the current drive power is high, the drive power
switch signal at the "H" level increases the delay amount of the output clock signal.
