A frequency/signal converter is provided that receives an input clock signal
and
generates an output signal. The converter includes a first circuit that receives
the input clock signal and generates first and second logic signals that are complementary
with one another, a loop circuit that includes a first circuit line and a second
circuit line that are each coupled between a first supply voltage and a second
supply voltage, and an integrator device. A current proportional to the output
signal of the converter flows in the loop circuit. The first and second circuit
lines include first and second capacitive elements and first and second switches
for interrupting current flow into the first and second capacitive elements, respectively.
The first and second switches are controlled by the first and second logic signals,
respectively. The first and second circuit lines are alternatively coupled to an
input terminal of the integrator device in order to obtain a substantially constant
voltage signal at the input terminal of the integrator device, and the integrator
device provides the output signal of the converter. Also provided is a switching
regulator for providing a regulated voltage to a load.
