A circuit for outputting area pattern bits from an area pattern array. The circuit
includes a first stage, second stage and third stage. The first stage is configured
to output N adjacent scan lines from a 2N2N area pattern array based on a
first address. N is a positive integer. The second stage is configured to receive
the N adjacent scanlines and to select an NN block from the N adjacent scanlines
based on a second address. The third stage is configured to (a) select an (N/2)N
region of bits from the NN block and load bits of the (N/2)N region
into a set of pixel tag outputs in a first mode, and (b) select an N(N/2)
region of bits from the NN block and load bits of the N(N/2) region
into the set of pixel tag outputs in a second mode.
