A dynamically configurable portion of a cache shared between central processing
and graphics units in a highly integrated multimedia processor is engaged as a
secondary level in a hierarchical texture cache architecture. The graphics unit
includes a small multi-ported L1 texture cache local to its 2D/3D pipeline
that is backed by the relatively large, single ported portion of the shared cache.
Leveraging the shared cache as a secondary level texture cache reduces system memory
bandwidth and die size without significant sacrifice in performance.
