A method and apparatus for providing full accessibility to on-chip instruction
cache and microcode ROM are described. A dummy tag and a dummy instruction are
written into a cache tag array and an instruction array, respectively, during a
test mode. The dummy tag is concatenated with a predetermined set number and a
predetermined word address to form a dummy address having a dummy tag field, a
set field and a word address field. An instruction fetch is invoked using the dummy
address. The instruction cache is accessed with the dummy address, and a cache
miss is forced to occur. The dummy tag field of the dummy address is written into
the tag array at a row specified by the predetermined set number, and the dummy
instruction is written into the instruction array at the same row. Execution of
the dummy instruction is suppressed. A read operation is performed in a similar
manner, except in that case an instruction cache hit is forced to occur to cause
data to be read from the instruction cache. Execution of the data read from the
cache is suppressed. Microcode ROM is also read by invoking a dummy instruction
fetch. The dummy instruction fetch causes data to be retrieved from a predetermined
address in the ROM. Execution of the retrieved data is suppressed.
