A buffer memory with a memory allocation and de-allocation circuit. The buffer
memory has an address space divided into address blocks and a memory address space
divided into memory blocks. The circuit, in response to an allocation request for
an allocation of a certain size buffer, allocates sufficient address blocks and
memory blocks for the buffer. The circuit, in response to a de-allocation request
to de-allocate a certain size of memory, de-allocates whole unused address blocks
and memory blocks.
