Cache coherence directory eviction mechanisms for unmodified copies of memory lines in multiprocessor systems

   
   

Cache coherence directory eviction mechanisms are described for use in computer systems having a plurality of multiprocessor clusters. Interaction among the clusters is facilitated by a cache coherence controller in each cluster. A cache coherence directory is associated with each cache coherence controller identifying memory lines associated with the local cluster which are cached in remote clusters. The cache coherence controller is operable to initiate eviction of an entry in its directory corresponding to an unmodified copy of a memory line by sending a request to write to the memory line to a corresponding memory controller.

 
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< Semiconductor memory device

< Program control flow conditioned on presence of requested data in cache memory

> Multiprocessor cache coherence system and method in which processor nodes and input/output nodes are equal participants

> Extending the functionality of a multi-functional apparatus

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