Memory cells each include a latch having storage nodes of data, and ferroelectric
capacitors connected to the storage nodes at one ends, respectively, and to a plate
line at the other ends. An operation control circuit performs volatile and nonvolatile
write operations. A plate driver sets the plate line at a predetermined voltage
so that a voltage exceeding a coercive voltage is applied between electrodes of
the ferroelectric capacitor connected to either one end of the latch during the
volatile write operation. Here, the latch retains the write data. It is therefore
possible to dispense with a circuit generating a voltage lower than or equal to
the coercive voltage and a circuit for switching voltages. This also eliminates
the need for power supply line of the voltage lower than or equal to the coercive
voltage, making the wiring area unnecessary. Consequently, the ferroelectric memory
can be reduced in chip size.
