Embodiments of the present invention include a memory controller that
provides memory line caching and memory transaction coherency by using at least
one memory controller agent. The memory controller includes at least one memory-controller
agent, an incoming memory-transaction dispatch unit, and an outgoing memory-transaction
completion unit. Each memory-controller agent has a memory-line memory controller
and a memory-line coherency controller, along with a cache memory capable of caching
the contents of a memory line along with coherency information for the memory line.
Memory transactions are received from cacheable entities of a computer system at
the incoming memory-transaction dispatch unit, and are then presented to one or
more agents. If multiple memory-read transactions are received for a single memory
line, the agents will configure themselves into a linked list to queue up the requests.
