A method of and apparatus for improving the efficiency of a data processing system
employing a multiple level cache memory system. The efficiencies result from enhancing
the response to SNOOP requests. To accomplish this, the system memory bus is provided
separate and independent paths to the level two cache and tag memories. Therefore,
SNOOP requests are permitted to directly access the tag memories without reference
to the cache memory. Secondly, the SNOOP requests are given a higher priority than
operations associated with local processor data requests. Though this may slow
down the local processor, the remote processors have less wait time for SNOOP operations
improving overall system performance.
