SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE INCLUDING MEMORY CELL SECTION HAVING CAPACITOR OVER BITLINE STRUCTURE AND WITH THE MEMORY AND PERIPHERAL SECTIONS HAVING CONTACT PLUG STRUCTURES CONTAINING A BARRIER FILM AND EFFECTING ELECTRICAL CONTACT WITH MISFETS OF BOTH MEMORY AND PERIPHERAL SECTIONS

The sheet resistance of a gate electrode 8A (a word line) of memory cell selection MISFET Q a DRAM and a sheet resistance of bit lines BL₁, BL₂ are, respectively, 2 / or below. Interconnections of a peripheral circuit are formed during the step of forming the gate electrode 8A (the word line WL) or the bit lines BL₁, BL₂ by which the number of the steps of manufacturing the DRAM can be reduced.