A method of designing and fabricating a control unit for electronic microcontrollers
or microprocessors that includes fabricating a finite state machine having at least
one combinatorial network, the finite state machine having a plurality of control
subunits, each control subunit structured to correspond to one combinatorial logic
network. Each unit in the plurality of control subunits is independently connected
to an arbitration block to provide information about a possible future state and
to receive a present state command.
