In an information processing device, a first address adder generates a first address representing a target for write of data or a storage location of data to be read. A second address adder generates a second address by adding 8 to the first address. First to seventh selectors appropriately select either the first address or the second address, and supply the selected address to first to seventh memory areas, respectively. An eighth memory area is supplied with the first address.

 
Web www.patentalert.com

< Method and apparatus for patching code and data residing on a memory

< Computer file management system

> Method and apparatus for automatically adapting a node in a network

> Rapid fail analysis of embedded objects

~ 00200