An electronic device for data processing may include p synchronous processor cores each respectively clocked by one of p clock signals all having a same period T and being phase-shifted by 2/p relative to one other. The electronic device may further include a single access shared memory with an access time less than or equal to T/p. The memory may be clocked by an access signal with a period T/p and that is synchronous with the clock signals. The processors cores may sequentially and cyclically access the memory at consecutive intervals spaced apart in time with a period equal to T/p. The electronic device is particularly well suited for use in audio processors of digital versatile disk (DVD) decoders, for example.