In each sampling period, sample data and a count value WA of a ring buffer counter 11 are supplied to a RAM 202 through a bus control circuit 14 as write data and a write address. Each cache block stored in a data buffer DB.sub.0 and so on is used for executing an FIR filtering operation. As an amount of unused sample data in the cache block is decreased, subsequent cache blocks used for a subsequent FIR filtering operation are supplemented to the data buffers DB.sub.0 and so on by the cache counter units CC.sub.0 and so on.