The occurrence of invalid data transitions on an output data bus (17) are reduced with an improved data sensing circuit (20). In a single block memory application, a self-controlled sense amplifier (21) eliminates the need for external timing control signals by triggering off the rail-to-rail voltage swings of a complementary bit line pair (BIT, BITB) of a memory array coupled to the inputs of the amplifier (21). Triggering off the bit lines (BIT, BITB) ensures that the amplifier (21) is not activated until valid data appears at its input, thereby preventing glitches on the output data bus (17) due to the amplifier (21) or associated latch (13). In a multiblock memory application, the data sensing circuit is further improved by eliminating invalid data transitions from appearing on the output data bus (17) through use of feedback. Data storage devices (13) of inactive blocks are preloaded with the valid data appearing on the output data bus (17) via a feedback circuit (23), thereby preventing potentially invalid data otherwise stored in an in active storage device (13) from being transferred to the output data bus upon activation.