A read/write scheduling apparatus of controller chip and method for the same. The read/write scheduling apparatus is used for arbitrating a plurality of read and write requests from a CPU to access a memory unit. The read request has higher priority in a host bandwidth limited case and the write requests in write queues are not sent until a predetermined amount of write requests are accumulated. In a DRAM bandwidth limited case, the read and the write requests have the same priority. The scheduling apparatus counts the number of the read and write requests to the memory unit within a predetermined time, the operation is changed to DRAM bandwidth limited case in case that the counted number is larger than a predetermined number.