A DRAM (dynamic random access memory) device has: DRAM with a self-refresh function; a DRAM controller for controlling the DRAM; a timer built in or externally connected to the DRAM controller; and CPU for controlling the whole device. In the DRAM device, the DRAM controller monitors access from the CPU to the DRAM and, when there is no access to the DRAM within the time set in the timer, the DRAM controller switches a refresh mode to the self-refresh mode.