A library tool suite supplements conventional design tools to increase the speed,
automation and accuracy of creating physical designs for a library of cells to
be used in chip designs. The tool suite may include a post operations tool, an
audit tool, a custom interface, a setup file and a place and route model preparation
utility which interact with the conventional tools and design data to automate
and ensure integrity of the physical design process. The tool suite facilitates
automatically generating libraries corresponding to an overall cell plan, generating
attributes defining strength of connection between possible pin placements within
a cell to facilitate routing inter-cell nets through a cell, and auditing cells
for errors prior to inclusion in a manufacturing library.