A method and a processor for processing two digital video signals clocked by respective clock signals of identical frequency but with a constant phase shift therebetween. Standard definition and progressive scan digital video signals which are clocked at first and second clock signals CLOCK1 and CLOCK2, respectively, of identical frequency with a constant phase shift therebetween are interfaced with a processing circuit (7) by an interface circuit (10). The progressive scan signal is clocked into a first register (20) on the second clock signal CLOCK2, and is clocked to a second register (21) by the first clock signal CLOCK1 and in turn to a third register (22) by the first clock signal CLOCK1. The edge of the first clock signal CLOCK1 on which the progressive scan signal is clocked into the second register (21) is chosen to allow sufficient time to clock the signal. The standard definition signal is clocked through fourth, fifth and sixth registers (23, 24, 25), respectively, and both signals are clocked from the third and sixth registers (22, 25) on the first clock signal CLOCK1 into the processing circuit (7).

 
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