A processing circuit for motion compensated de-interlacing of video signals, having a line memory 21, a de-interlacing circuit 22, a frame memory 24, and a cache memory 25, further includes a pixel mixer 29 interposed between the cache memory 25 and the de-interlacing circuit 22.

 
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> Apparatus and method of controlling image display

> Television analogue and digital convertor apparatus

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