A multi-way set-associative cache memory is configured to operate only with those ways of the tag and data memories that operate normally, and excludes those ways of the tag and data memories that are determined to be incurably defective. By reducing the size of the cache memory to exclude the defective cells, the present invention is capable of preventing scrapping or discarding of the entire high-priced processor chip in which CPU and cache memory are integrated into a single chip.

 
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< Disk subsystem

< Read access and storage circuitry read allocation applicable to a cache

> Management of caches in a data processing apparatus

> Non-speculative distributed conflict resolution for a cache coherency protocol

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