A peripheral bus switch that is adapted to connect together a pair of electrically independent peripheral buses to which arrays of peripheral devices (e.g. hard disk drives) are respectively connected in a peripheral bus interconnect system to ensure continuous access to all of the peripheral devices in the event that one of a pair of peripheral bus controllers which drive the peripheral buses should malfunction and require shutdown. The peripheral bus switch is a normally open switch that is connected between the pair of independent peripheral buses. In response to a malfunction, such that one of the pair of peripheral bus controllers fails to generate a timely health check report signal, the properly functioning peripheral bus controller will generate a power down signal to shut down the malfunctioning controller and a bus control signal to cause the normally open peripheral bus switch to close, whereby the properly functioning controller can access the arrays of peripheral devices connected to the pair of peripheral buses without interruption and as if no malfunction had occurred.