A image displaying and controlling apparatus for displaying a computer graphics image in square-shaped pixels in an MPEG2 image format in rectangular-shaped pixels at a regular roundness. A graphics processor block produces the data of 640480 pixels, two-line data of which are stored in two 1H buffers, and are multiplied respectively by weights output by a weight control circuit through a line conversion circuit. As a result, data of 640432 are produced. A delay circuit delays a vertical synchronizing signal output by the graphics processor block by 14H. A phase comparator circuit compares the 14H delayed vertical synchronizing signal in phase with a vertical synchronizing signal output by an MPEG2 video decoder. The timing of the generation of the vertical synchronizing signal at the graphics processor block is set to be earlier by 14H than the timing of the generation of the vertical synchronization signal of the MPEG2 video decoder. The memory capacity required of the buffers in front of the line conversion circuit in a processing circuit is for two lines only while line conversion process is performed without any destruction of pixel data.