Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules are disclosed. In one particular exemplary embodiment, the techniques may be realized through a memory system comprising a memory module and a memory controller. The memory module comprises a memory component with a memory core for storing data therein. The memory controller comprises a first set of interface connections that provides access to the memory module, a second set of interface connections that provides access to the memory module, and memory access circuitry that provides memory access signals to the memoory module for selecting between a first mode wherein first and second portions of the memory core are accessible through the first and second sets of interface connections, respectively, and a second mode wherein both the first and second pertions of the memory core are accessible through the first set of interface connections.

 
Web www.patentalert.com

< Semiconductor memory device with fast masking process in burst write mode

< Host adapter integrated data FIFO and data cache and method for improved host adapter sourcing latency

> Method and system for backing up data of data processing devices including fixed length block format data conversion to variable length block format

> Method and apparatus for scheduling of requests to dynamic random access memory device

~ 00218