A data carrier (2) or an integrated circuit (41) for a data carrier (2) comprises a memory (54) which is designed to store intermediate operating state information (ZS, CI16, CI20, BRS) significant for an intermediate operating state of the data carrier (2) or the integrated circuit (41) and comprises a memory control device (51), which after the occurrence of information significant for intermediate operating states ensures that this intermediate operating state information is stored in the memory (54) and comprises a control device (51), which—after the detection of the non-existence of the supply voltage (V) required for faultless operation during execution of a communication sequence interrupted by this non-existence and the subsequent detection of the re-existence of the supply voltage (V)—ensure that the data carrier (2) or the integrated circuit (41) is controlled in an intermediate operating state for which intermediate operating state information (ZS, CI16, CI20, BRS) stored in the memory (54) is significant.