Address based prefetch logic varies prefetching according to address values
in read requests. The address based prefetch logic can vary how much data is initially
read into a prefetch buffer or when a prefetch buffer is refilled to an initial
prefetch amount. One advantage of the address based prefetch logic is that prefetching
and prefetch buffer refill rates are tuned for particular application. This is
important since the system controller ordinarily does not know how much data the
master is requesting beyond the first data phase. The requested read address is
used as a hint to determine how much prefetching needs to occur. Over prefetching
wastes memory bandwidth, and potentially adds latency to other masters sharing
common busses. Under prefetching may cause the system controller that is acting
as a PCI target to terminate the master's read request, thus wasting PCI bandwidth,
adding latency.