512 clusters included in one segment are distributed into 128 clusters included in each of four storages. A logical/physical address conversion table is formed every segment. Therefore, unless the segment is changed, the logical/physical address conversion table to be referred to or updated does not change, so that a deterioration of the reading performance due to an access to the table or an updating of the table can be prevented. Data can be simultaneously written into continuous logic cluster addresses, for example, 0x0004 to 0x0007, and the high speed writing operation can be realized.

 
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< Signal input and output apparatus that discriminates between plurality of different devices each issuing unique control signals substantially simultaneously through single transmission path

< Data playing system, transmitting and receiving apparatus, and bus conversion unit

> Multi-sequence burst accessing for SDRAM

> Signal processing circuit

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