A method and system are disclosed to optimize an integrated circuit layout design by determining possible lengths of layout rows that will reduce the total area of the integrated circuit layout (FIG. 4B). The possible row lengths (401B) are determined and stored in a memory unit as a set of possible optimal row length values. A set of possible optimal row heights corresponding to the determined set of possible rowlengths is determined and the total chip area is iteratively calculated. Optimal values of rowlength and row height are chosen based upon the maximum chip area reduction. Once the optimal row length and height parameters are chosen, transistor devices placed in each row of the integrated circuit layout are folded to achieve the optimal row length and height.