Techniques are disclosed for initializing a representation of a cache
in a microprocessor design under test. The cache representation includes a plurality
of cache entries, each of which is uniquely referenced by an address-way pair.
A test case includes a plurality of cache initialization records, each of which
includes a cache entry reference and an initial cache entry value. Each cache entry
reference includes an address identifier and a way identifier. An initializer reads
the cache initialization records and uses the records which contain valid address-way
pairs to initialize cache entries in the cache representation. The initializer
then uses the remaining records, in which the way identifier is an invalid (e.g.,
null) value, to initialize cache entries in the cache representation. Valid way
identifiers are selected for these records in a manner which ensures that cache
entries are not initialized more than once.