A signal processing apparatus includes a digital signal processor (DSP) including an internal memory part storing a program to carry out, an external memory part storing all programs to carry out in the DSP, a clock signal generating part for generating and outputting a clock signal to the DSP, and a clock signal control part for controlling to output said clock signal to the DSP. More particularly, the clock signal control part forwards the programs outputted from the external memory part to the internal memory after the clock signal generating part stops outputting the clock signal to the DSP.