A nonvolatile ferroelectric memory device and a method for writing and reading multiple-bit data using the same, in which multiple bit data is stored in one cell to reduce a cell layout area, thereby obtaining price competitiveness of a chip. The nonvolatile ferroelectric memory device includes a sensing amplifier block having multiple sensing amplifiers comparing multiple-level signals from main bitlines and sensing them in a multiple-bit, the sensing amplifiers being commonly used in a multiple cell array blocks to feed the sensed multiple-bit levels back and restore them in a cell, and switching transistors arranged one by one per sub bitline to sense data values of the unit cell.