A memory controller includes a threshold register that stores a value indicating a length of time and a control unit. In response to a first memory access request, the control unit generates signals that cause a memory device to open a page of memory. The control unit generates signals that cause the memory device to close the page if the page has been open for the length of time indicated by the value in the threshold register. The control unit modifies the value in the threshold register in response to receiving a second memory access request. For example, if the second memory access request causes a page miss for a most recently open page, the control unit may increase the value in the threshold register. The control unit may decrease the value in the threshold register in response to a page conflict caused by the second memory access request.